BIOS release note

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DBR36238.ROM	Date:06-23-2008	Rev 2.1

1. a)Updated Intel ESB2 AHCI firmware to v1.17d.
   Description:	Fixed 2 bugs that resulted fail to boot to ODD in Port1 and beyond.
   Validation:	Check AHCI banner after enabled "SATA AHCI Enable" item in BIOS Setup.

2. Implemented SLP2 module replacable by Phoenix BIOSEdit.
   Description:	This feature aids in supporting OEM SLP2 modules by Phoenix
                BIOSEdit.
   Validation:	Follow the SOP document.

3. Implemented "Windows Hardware Error Architecture" for Windows Server 2008.
   Description:	This feature is a requirement for Windows Server 2008 Logo.
   Validation:	Run DTM program with Windows Server 2008.

4. Implemented new Thermal Guideline with Tcontrol concepts in Intel CPUs.
   Description:	Intel Core-Architecture processors introduced relative
                temperature for thermal concepts. Displaying absolute
                value violated processor specification.  Basically,
                absolute value is nothing to do with CPU temperature.
                New thermal guideline is changed to display thermal
                text by adopting CPU Tcontrol concepts.
                * Low is displayed whenever PECI count is less than Tcontrol-10.
                * Medium is displayed whenever PECI count is within Tcontrol-10 ~ Tcontrol.
                * High is displayed whenever PECI count is more than Tcontrol.
                * OH Alert is triggered upon Tcontrol+5
                * Tcontrol and PECI count are displayed if both RI# and PME# triggered.
   Validation:	Please refer to new Thermal Guideline for how to
                validate this feature.

5. a)Fixed CPU temperature became N/A after ICHOFF overnight.
   Description:	Lab found CPU temperature became N/A after doing ICHOFF
                overnight.  In most cases, CPU1 presents this scenario.
   Validation:	With this BIOS, the issue won't happen any more.
   b)Disabled FANIN9 & FANIN10 sensor by default.
   Description:	Per Dony, FANIN9&FANIN10 are no-connect (viz. floating) on
                most designs.  BIOS may enumerate fan9 & fan10 existence due
                to the noises.
   Validation:	Check W83793 REG58<5,3>=0,0 and REG5C<4:3>=00.

6. Implemented IPMI Set LAN Configuration via BIOS Setup.
   Description:	Customer requested to configure IPMI IP, MAC, Subnet mask,
                default gateway and VLan ID via BIOS Setup instead of DOS
                utilities.
                BIOS is able to read current LAN settings from IPMI and
                displays in BIOS Setup. User can change those and BIOS
                writes back IPMI.
   Validation:	Enter BIOS Setup with IPMI installed. BIOS displays LAN
                settings as same as those in IPMI browser. You can change
                those settings in BIOS Setup and Save & Exit. IPMI browser
                refreshes to show the same settings.

8. Fixed unexpected FSB IERR assertion.
   Description:	CPU IERR# pins wired to south bridge PIRQ<H:G>/GPI<5:4> pins.
                IERR# may get asserted if PIRQ<H:G> activated.  Changed to
                GPI<5:4> for the fix.
   Validation:	Check GPIO 0x1080<5:4>=11.

9. Fixed POST 49h hung on X7DAL+/X7DA8+ series with 4GB RAM and Dempsey CPUs.
   Another scenario: Addon option ROMs can not activate with 4GB RAM and Dempsey CPUs.
   Description:	It is because MTRR settings conflicts between primary and secondary
                threads when 4GB RAM installed.  A bug since 2.0b.
   Validation:	Try 3ware/LSI storage cards and check their ROM activation on Server
                board.  Boot X7DAL+/X7DA8+ with Audio enabled and system won't hang
                at POST 49h.

11.Fixed POST 49h hung with 4GB RAM if "Discrete MTRR Allocation" sets to Enabled.
   Description:	It is because MTRR settings conflict among cores or threads when 4GB
                 RAM installed.  A bug since 2.0b.
   Validation:	Boot X7DAL+/X7DA8+ with Audio enabled and "Discrete MTRR Allocation" enabled.
                System won't hang at POST 49h.

12.b)Fixed SUSE Linux 10 SP1 complained "ib_mthca 0000:06:00.0: 
     BIOS or ACPI interrupt routing problem" on X7DBT.
   Description:	The IB driver can not be loaded on X7DBT during installing
                SUSE Linux 10 SP1. The message "ib_mthca 0000:06:00.0: 
                BIOS or ACPI interrupt routing problem" is posted.
   Validation:	With this BIOS, the IB driver can be loaded correctly.

13.a)Defaulted System Date to 07/01/2008 if CMOS low.
   b)Updated Intel Xeon micro-code.
     - Rev A07 for Harpertown E-0 stepping 1067Ah.
     - Rev A07 for Wolfdale-DP E-0 stepping 1067Ah.
   Description:	Intel will release Xeon E-0 stepping.
   Validation:	Run mcu_sig.exe in DOS or CPU-z in Windows with the CPU installed.

16.a)Update to BIOS Rev 2.1.
   b)Fixed asset tag field missing in SMBIOS Type2 per DTM.

17.Fixed system hanged when updating CPU microcode via INT 15h interface.
   Description:	Run Intel checkup7 tool with old BIOS and Xeon E-0 in DOS. System
                hanged upon loading the CPU microcode.
   Validation:	With this BIOS, checkup7 tool won't cause a hung.

18.Fixed HDD Pre-Delay feature broken.
   Description:	This issue was found when doing OEM BIOS.  The feature
                is not enabled in official build.
   Validation:	None

19.Fixed USB CD-ROM not able to booted if QLogic iSCSI firmware activated.
   Description:	USB CD-ROM can not boot to CD media after QLogic iSCSI
                firmware activated with drives attached.
   Validation:	With this BIOS, USB CD-ROM still boots when QLogic iSCSI
                exists.

20.Fixed FreeBsd 7.0 installer reported errors by dumping CPU registers
   when booting from USB CD-ROM.

21.Fixed intermittent "System Configuration Data Read Error" message in POST.

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DBR36108.ROM	Date:06-10-2008	Rev 2.0c

1. Fixed user's UCR settings altered after AC lost and recovery.
   Description:	It is the side-effect of 3208.Fix#5. With IPMI existence,
                user's console redirection settings are changed after AC
                lost and recovery.
   Validation:	Boot system with IPMI installed and enter BIOS Setup with
                3208 BIOS.  UCR is COM2, 115200 at this point.  Change those
                to any other values and Save Changes.  Remove AC cord and
                reapply it in one minute.  Enter BIOS Setup again and UCR
                setting incorrectly gets back to COM2, 115200.
                With 6108 BIOS, UCR setting remains as what it was before
                AC lost.

2. Update to BIOS Rev 2.0c.

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DBR33208.ROM	Date:03-20-2008	Rev 2.0b

1. Fixed POST screen corrupted when displaying SMART drive failure message.
   Description:	POST screen was corrupted when BIOS detects and displays SMART
                drive failure message.  It was a side-effect after implemented
                the feature of logging SMART drive failure into IPMI.
   Validation:	Attach a IDE/SATA HDD that generates SMART drive failure. POST
                screen is not corrupted with this BIOS.  Validated by Hang Loo Tang.

2. Fixed BIOS incorrectly showed 3.20GHz string for 3.16GHz processors.
   Description:	3.20GHz was displayed in POST screen, BIOS Setup and Summary Table
                for 3.16GHz processors.
   Validation:	Check those three areas with this BIOS.  Validated by Hang Loo Tang.

3. Fixed RAID size limited to 2TB with AOC-USAS-S4iR/S8iR card when creating
   RAID by Adaptec Storage Manager.
   Description:	This scenario was observed on X7DBU when a RAID size larger than 2TB
                was created by AOC-USAS-S4iR firmware.  In Windows, you need to convert
                such big volume into GPT format in Computer Management -> Disk Manager.
                Adaptec Storage Manager remained busy or reported 2TB less volume after
                deleted and recreated a new RAID.
   Validation:	ASM no longer encounters those scenarios with this BIOS.
                Validated by Hang Loo Tang and John Chen.

4. Don't wait for <F1> key upon SMART drive failure if "Post Error" item sets to Disabled.
   Description:	BIOS always halted and waited for <F1> key regardless "POST Error"
                setting in Setup after displayed SMART drive failure message.
   Validation:	With this BIOS, system continues to boot if "POST Error" sets to Disabled.

6. Don't insert new detected device onto top 8 boot candidate list in Setup.
   Description:	New detected boot device was inserted into 8 boot-candidate list in Setup
                if there was an empty slot in the list.
                It is a side-effect of the kernel code update in 2228 release. The scenario
                was different from all previous BIOS builds.
   Validation:	With this BIOS, the new detected device stays where it did. For example,
                USB LS-120 type is out of top 8 boot-candidate list, which contains one empty
                slot and new inserted USB LS-120 drive will stay out of the list.

8. Fixed BIOS incorrectly returned SW_ALL for EIST _PSD method for Quad-Core processors.
   Description:	By running Linux FIrmware Kit v3.0, EIST _PSD method was found to
                incorrectly returned SW_ALL for multi-core processors.  SW_ALL
                should be returned when OS claims the support.
   Validation:	Download the kit from http://linuxfirmwarekit.org.  Boot to the kit
                with EIST enabled in BIOS.

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DBR32258.ROM	Date:02-25-2008

1. Patched some Intel Harpertown returned inproper and solid high temperature.

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DBR32228.ROM	Date:02-22-2008

1. a)Updated Intel ESB2 AHCI firmware to v1.12e.
   b)Updated Intel ESB2 RAID firmware to v5.6.4.1002.

3. Applied CPU temperature offset by using the value from processor.
   It gets reasonable temperature values with Harpertown/Wolfdale-DP.

4. a)Supported SMBIOS v2.5.
   b)Stored BIOS revision into SMBIOS Type0.
   c)Extended SMBIOS Type11 fields to 32-byte wide.

6. Configure PCI-e payload size per "PCI-e I/O Performance" BIOS item.

7. Fixed intermittent POST hung at 0Ah after clear CMOS.

8. a)Fixed TFTP download failed when booting to WDS server.
   b)Default Date to 01/01/2008 if CMOS low.

9. Fixed no L2 information when Harpertown/Wolfdale-DP installed.

10.Update to BIOS Rev 2.0b.

12.Send Smart Drive Failure event into IPMI when occurs.

13.Updated to Intel MRC v1.32.

14.a)Fixed Direct Cache Access not working with Harpertown/Wolfdale.
   b)TM2 feature never be enabled with Harpertown/Wolfdale when CMOS sets so.

15.Updated Intel Xeon micro-code.
   - Rev 69 for Clovertown B-3 stepping 6F7h.
   - Rev CD for Woodcrest B-2 stepping 6F6h.
   - Rev 60B for Harpertown C-0 stepping 10676h.
   - Rev 60B for Wolfdale-DP C-0 stepping 10676h.

16.FreeBsd does a sanity check on the checksum field in $PIR table.

17.Fixed Linux kernel reported "PCI: BIOS Bug #81" in dmesg. 

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DBR3C037.ROM	Date:12-03-2007

1. a)Patched Harpertown C0-Step 2.5GHz might hang at POST 49h for SMM L1 init.
   b)Fixed 2.53GHz incorrectly displayed for 2.5GHz CPU.

2. Fixed onboard LAN failed to boot if one card with P2P bridge
   plugged before its parent bridge.

4. Update to BIOS Rev 2.0a.

5. Fixed Machine Check not configure properly for Harpertown/Wolfdale-DP.

6. Corrected HDD Information under Setup upon loading defaults by <F9>.

7. Improved CDROM-BOOT Function.

8. Updated the workaround for revised Errata #24 in MCH BSU v1.04.
   - For PCI-e port configure as:
      x4 (port 0,2,4,6) then program D[6,4,2,0]:F0:Offset_22Ch[19:14] to 2
      x8 (port 2,4,6) then program D[6,4,2,0]:F0:Offset_22Ch[19:14] to 2
      x16 (port 4) then program D[6,4,2,0]:F0:Offset_22Ch[19:14] to 2

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DBR3B027.ROM	Date:11-02-2007

2. a)Fixed overheat LED might blink upon entering OS.
   b)Applied +10'C offset for Harpertown CPUs.

3. a)Fixed CPU Temp 1 reported minus value at first few seconds
     when displaying SDR in IPMI Setup.
   b)Fixed BIOS displayed Sensor Number as CPU Temp1 and Event 
     Description as Unspecified in IPMI Setup for POST Error SELs.
     - Sensor Number changed to 0xFF (Unknown).  Need IPMI FW to fix.
     - Event Description changed to OEM.
   c)Fixed BIOS displayed Sensor Number as CPU Temp1 in IPMI
     Setup for POST Progress SELs.
     - Sensor Number changed to 0xFF (Unknown).  Need IPMI FW to fix.
   d)Fixed forced PXE boot via IPMI Get Boot Option not working.
     - How to test:
      Enable PXE ROM in BIOS.
      gstoolp -im 20 00 08 04 01 01
      gstoolp -im 20 00 08 05 80 04 00 00 00
      gstoolp -im 20 00 02 03

4. Supported Intel processor N/2 ratio.
   - This allows to select x.5 core-to-freq ratio.
     Eg, 2.83GHz is 333MHz multiply 8.5.

5. a)Configured PCI-e Max. Read Request Size to 4096B.
     - For better PCI-e performance.
   b)Send BMC SMB Request CMD prior booting.
     - It fixes SMBus conflict between IPMI and CentOS.

6. Fixed Intel ESB2 SATA RAID not auto-rebuilding upon degrading.
   - Intel Matrix Manager gets notified right away if RAID degrading.

7. Supported MTRR with 38-bit addressing (cache settings).
   - Woodcrest/Clovertown G0, Harpertown, Wolfdale enables 38-bit PAE.

8. Fixed wrong IRQ entry in MP table for devices behind multiple
   levels of non-embedded P2P bridges.

10.Configure PEXH Payload size per "PCI-e I/O Performance" item.

11.a)Updated Intel Xeon micro-code.
     - Rev B7 for Clovertown G-0 stepping 6FBh.
     - Rev B7 for Woodcrest G-0 stepping 6FBh.
     - Rev 606 for Harpertown C-0 stepping 10676h.
     - Rev 606 for Wolfdale-DP C-0 stepping 10676h.
   b)Don't write PCI information into ESCD.
     - It allows to support dozens of PCI cards with a hung.

13.Updated Processor Power Management codes for C-State.

14.Fixed FBD DIMM manufacturer and series number not stored in
   in SMBIOS Type 17 if one of those SPD bytes is a zero.

15.Fixed POST hung at E6h intermittently when enabling clock
   spread spectrum feature.

16.Fixed CMP disabling not working with Clovertown and Wolfdale-DP.

17.Update to BIOS Rev 2.0.

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DBR38137.ROM	Date:08-13-2007

1. Applied temperature offset -7'C instead of -13'C for Woodcrest/Clovertown/Harpertown.

3. Changed PCI NMI handler so it preserves PCI INDEX register.

4. Fixed some W39V080FAP/FAPZ parts not reliable when updating BIOS via phlash16.
   - Added delay according to Winbond's application note.

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DBR38097.ROM	Date:08-09-2007

1. Supporting Harpertown/Wolfdale-DP processors.
   - Rev 106 for Harpertown A-1 stepping 10671h.
   - Rev 404 for Harpertown B-0 stepping 10674h.
   - Rev 106 for Wolfdale-DP A-1 stepping 10671h.

4. Armed SERIRQ SMI events specified to W83627DHG.
   - SERIRQ SMI was incorrectly armed for boards without W83627DHG.

6. Fixed Fan-Failure events intermittent triggered in OS.
   * Side-effect of 4207.3a.

7. a)Supported to access SMBus interface via IPMI, if existed, when fan fails.
   - Preventing SMBus conflict between BIOS and IPMI.
   b)Initializing IPMI if it got reset by BMC command.
   - BIOS can not know whether IPMI gets reset by BMC command, so BIOS proceeds
     IPMI initialization every POST.
   c)Set to 115200 baudrate for PepperCon BMC.
   - Per IPMI team and PM.  Early/Old IPMI cards which only support 19200 baudrate may fail SOL.

8. Fixed LSI SAS31601E firmware incorrectly activated when BIOS sets to disable.

9. Fixed onboard LAN failed to boot if one card with P2P bridge plugged 
   before its parent bridge.
   - For example: Plugging Matrox PCI-e x1 G550 video in PCI-e x4 slot caused
     onboard LAN failed to boot.

10.Add workaround for MCH BSU v1.03 Errata #24.
   - For PCI-e port configure as:
      x4 (port 0,2,4,6) then program D[6,4,2,0]:F0:Offset_22Ch[19:14] to 1
      x8 (port 2,4,6) then program D[6,4,2,0]:F0:Offset_22Ch[19:14] to 3
      x16 (port 4) then program D[6,4,2,0]:F0:Offset_22Ch[19:14] to 7 

11.Add workaround for ESB2 Errata #100.
   - Set BusM_Dev0_Func0_Reg42<1>.

12.a)Default Date to 07/01/2007 if CMOS low.
   b)Updated Intel Xeon micro-code.
     - Rev 67 for Clovertown B-3 stepping 6F7h.
     - Rev C9 for Woodcrest B-2 stepping 6F6h.
     - Rev B4 for Woodcrest G-0 stepping 6FBh.

13.Supported mixed stepping for Clovertown or Woodcrest.
   -This feature allows you to install one Clovertown G0 Step with one B3.
   -This feature allows you to install one Woodcrestn G0 Step with one B2.

14.Recorded more FBD information in SMBIOS Type 17 per DIMM.
   - FBD DIMM size, manufacturer, series number, part number will be
     stored in SMBIOS Type 17 if DIMM vendor burns those in SPD.

16.Update to BIOS Rev 1.3c.

17.Added BWA for ESB2 Spec Update Errata #99.
   - The ESB2 requires the Other Interrupt Control Register be read
     after the APIC Enable bit is modified.

18.Put double I/O delays at 3 locations in PreShadBridgeReset routine.  It
   should get away from intermittent IERR assertion at early POST found on
   some Hitachi HA8000 boards.

20.Fixed Sony SDX-5xx Tape drive not recognized.

21.Fixed the bug that system hangs if memory single bit error on Linux EMT64T.

22.Fixed <ESC>+<!> for F11 hotkey not working via UCR.

23.Fixed missing DW (terminate word) in DMI type 37 and 38.
   - Vista Logo program found this bug.

24.Fixed ACPI _PSD reported inproper domain# for CPU proximity.

25.PXE ROM hangs upon first boot after flashing with CMOS cleared.

26.Fixed TFTP download failed after booting to Windows Deployment Services.
   * Side-effect of 4207.12.

27.Defaulted to Coalesce for PCI-e I/O Performance option.
   - Coalesce mode prevents the unreliable issue with many PCI-e cards.
   - Customer needs to set Payload 256 for better PCI-e performance.

28.De-featured ACPI SLIC table.

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DBR35297.ROM	Date:05-29-2007

1. Fixed a variety of issues with BIOS v1.3a.
   - Onboard SCSI option ROM failed to activate.
     * Side-effect of 4207.1.
   - POST hung at 55h with PCI-e video and onboard SAS controller.
     * Side-effect of 4207.12.
   - Some USB devices malfunctioned when more than 4 existed.
     * Side-effect of 4207.14.

3. Update to BIOS Rev 1.3b.

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DBR35107.ROM	Date:05-10-2007

1. Updated Adaptec ESB2 SATA HostRaid b2229.

2. Updated Intel Memory Reference Code v1.31.

3. Fixed EIST no longer working since 4207 BIOS build.

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DBR35027.ROM	Date:05-02-2007

3. Added microcode Rev 0B4h for Clovertown G-0 stepping(6FBh).

4. Added SLIC table to support SLP2 activation.

7. System locked up with Clovertown G-0 stepping if MCU is loaded
   and CMP sets to Disabled.

8. Fixed Plextor PX-760A and PX-755SA not listed in boot menu even
   those are detected during POST.

9. Update to BIOS Rev 1.3a.

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DBR34207.ROM	Date:04-20-2007

1. a)Changed to use PXE split ROM.
   -It solved PXE ROM hanging after CMOS error and forced to boot.

3. a)Send INIT command to W83793G at early POST.
   -It solved inproper temperature from Dempsey.
   b)Fixed fan failure detection not working on X7DBR series.

4. s)Support NMI request from IPMI.
   b)Fixed UCR on COM2 not able to enable once disabled.

5. Add the following memory operation failures into event logging.
    - 02A8: Cannot enable Memory Mirror
    - 02A9: Cannot enable Memory Sparing on Branck 0
    - 02AA: Cannot enable Memory Sparing on Branck 1

6. Updated FBD frequency into SMBIOS Type17.

7. Changed Sensor Number to 0xFF for PCI and memory error SELs.
   -It solves IPMI viewer interpreted PCI and ECC errors from CPU1.

8. Added "PCI-e Link Width Workaround" item in BIOS.
   -This allows to skip three times of reset with non-G step MCH when
    PCI-e card link width not matched to MCH root port.

9. Fixed PCI Compliant Test failed with Windows Vista Logo.

11.Supported two USB virtual devices simulated by Peppercon BMC.

12.Optimized PCI memory allocation for 4G memory support.

14.Fixed BTX halt when booting into FreeBsd on USB key.

15.Updated Intel Memory Reference Code v1.30.

16.Fixed SLP function created by PLOGO not working since 1107 BIOS release.

17.Updated Intel Xeon micro-code.
   - Rev 66 for Clovertown B-3 stepping 6F7h.
   - Rev C6 for Woodcrest B-2 stepping 6F6h.

18.Updated Intel EIST codes for independent maximum VID.

19.Fixed BIOS reported "memory address fail at 0x1F" if PCI memory
   is larger then 2GB.

20.Update to BIOS Rev 1.3.

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DBR31267.ROM	Date:01-26-2007

3. Forced ESI interface to Coalesce mode with 128B payload.
   --It is mainly to solve PCI Parity Error from PCI devices behind
     ESB2 root port.  The hierachy looks like this:
     MCH ESI (128B or 256B) <--> ESB2 RP(hardwired 128B) <--> PXH PCIX (128B or 256B)
     Overflow can occur if both ends set to 256B.

4. Set PXH-V Reg40h<3> per Intel recommendation.

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DBR31197.ROM	Date:01-19-2007

2. Set Target Content Distribution bit in SMBIOS Type0 - BIOS
   Characteristic Extension Byte 2 Bit 2.
   --It is required for SMBIOS v2.4 per Vista Logo program.

7. Fixed memory absent beep not working with Woodcrest and Clovertown.

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DBR31107.ROM	Date:01-10-2007

1. Worked around PepperCon firmware not responding after it received
   new SVID&SID information and reset itself.
   --BIOS takes around 90 seconds to initialize SIM IPMI series after
     standby power reset.

2. Do a power-cycle after changed Intel VT option in Setup.
   --Was: Asking users to manually do a power-cycle.
   --Now: BIOS will auto-proceed it in case users not aware of this.

4. Replaced "Enable Multimedia Timer" with "High Precision Event Timer".
   --High Precision Event Timer is an official name of Multimedia Timer.

6. a)Applied BIOS workarounds for Intel 80333 I/O processor.
   b)Fixed wrong IRQ routing in MP table for PCI-e slot decoded by
     MCH Dev6 when "Emulated IRQ" enabled.
   c)Fixed missing HPET address in ACPI HPET table when "High Precision
     Event Timer" enabled.

7. Added Intel RAID firmware workaround.
   --Intel AHCI firmare is no longer activated prior Intel RAID one
     when enabled Intel RAID in Setup.

8. Ignore BIOS workaround #501592 for MCH B3~G1 stepping.
   --It skips 3 contiguous resets at POST 49h with certain
     PCI-e cards on MCH slots if MCH B3~G1 detected.

9. a)Added ESB2 documentation changed #2 from BSU 0.78.
   -- For PCI Express* switch upstream port (Bm:D0:F0) and downstream
      ports (Bp:D0/1/2:F0), offset 3Ch bits[15:8] (interrupt pin) have
      default attribute as RWO. BIOS needs to write them once to lock
      the values and change the attributes to RO.
   b)Fixed system hanged with Harris XD200 VGA when existing PCI-64 slot.

10.a)Default Date to 01/01/2007 if CMOS low.
   b)Removed useless ISA codes to save more spaces.

11.Returned ACPI HPET object with Disabled status if not Windows XP.
   --New ACPI-OSes other than Windows XP do not support ACPI HPET
     object but recognise ACPI HPET table.

12.Corrected SMBIOS Type32 structure.
   --Deleted surplus data bytes from structure.

14.Update to BIOS Rev 1.2b.

16.a)Routed POST codes to LPC interface in boot block.
   --POST codes within boot block are output to LPC instead of PCI
     interface.  Those within main BIOS are controlled by "Route 
     Port 80h cycles to".
   b)Set Top Swap Lock-Down bit, which prevents Top Swap bit from being changed.
   --Top Swap bit may incorrectly get set by software and processor
     will fetch wrong BIOS code to hang after reset.
   Note: /BBL parameter is required during flashing BIOS.

17.Fixed Woodcrest/Clovertown cache No-fill mode for MRC codebase setting error.
   --It speeds up MRC operation with Woodcrest/Clovertown.

18.Updated Intel Memory Reference Code v1.21.
   --MRC revision is self-modified to v1.21 with NEC AMB.

19.Patched RTC not ticking after battery lost recovery.
   --It solved a mystery issue in contracted manufacturers with POST
     hung 29h after boards assembled and first powered up.

20.Fixed SATA drives incorrectly ran under PIO mode when PATA is disabled.

22.Fixed IDE/SATA detection taking too long at POST 90h.

23.Added a timeout mechanism in SMBus access routines.  It was an
   endless loop in those routines.

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DBR3C056.ROM	Date:12-05-2006

1. Defaulted to PCI-X 100MHz for the bus with SAS and ZCR on X7DBR-3.
   User is allowed to select PCI-X 133MHz via BIOS Setup.

2. Updated to BIOS Rev 1.2a.

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DBR3B146.ROM	Date:11-14-2006

1. Rolled back Adaptec ESB2 SATA HostRaid b2130.

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DBR3B066.ROM	Date:11-06-2006

1. a)Updated Adaptec ESB2 SATA HostRaid b2229.
   b)ATi ES1000 video BIOS with yj22274a.cfg.

2. Add "PCI Fast Delayed Transaction" in Setup.  It helps some
   legacy PCI cards which desire heavy DMA loads in 64bit slots.

3. Allowed NMI generation upon PCI error occurrence if "PCI Parity
   Error Forwarding" set to Disabled.

4. Defaulted to Payload 256B for "PCI-e I/O Performance" option.

5. Fixed system hanged if some type of add-on card with P2P bridge
   embedded plugged in PCI-e slot from Intel 5000 chipset.

6. Fixed Linux ipmitool not working with PepperCon BMC.

7. Updated to 8192KB in SMBIOS Type7 for maximum L2 Cache size.

8. Reported "Intel 5300 Quad Core CPU not Supported" message if such CPU
   populated without MCH G-Step onboard.

11.a)Fixed MSR 0x1A0 and 0x1AA not consistent among processor cores.
   b)Fixed MSR 0x3A not restored to APs properly after S3.

12.Fixed INTIN[00:23] of 1st I/O APIC changed from 00000000_00010000
   to FF000000_00010000 since 8116 release.

13.NVRAM Manager wipes out interrupt vectors when no PMM conventional
   memory available.

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DBR3A186.ROM	Date:10-18-2006

1. Fixed BIOS displayed wrong IPMI information in Setup if
   "SYS Firmware Progress" enabled.

2. Add "Default Primary Video Adapter" in Setup.
   -Boards with onboard VGA include "Other" and "Onboard"(Default).
   -Boards without onboard ATi include "Other" and "PCI-e x16"(Default).

3. Add "Emulated IRQ Solution" in Setup.
   -When enabled, it can achieve the best throughput by distributing 
    unique 8 interrupts of multiple PCI-e I/O cards to all 8 cores of
    dual-Clovertown.  Please refer to "Emulated IRQ Solution for Intel
    5000 Series base Platformw" white paper.    

4. Defaulted to enable "Execute Disable Bit" BIOS option.
   -Windows Server edition will auto-enable /PAE (Physical Address Extension)
    in kernel if /DEP (Data Execution Prevention) option is applied in boot.ini
    with Executed Disabled feature armed in Processor.

5. Fixed system auto powered-up with PepperCon IPMI after Windows shutdown.

6. Fixed PXH PCIX frequency control/information missing with add-on
   P2P bridge since 9196 release.

7. a)Fixed system not continued to boot when "POST Error" sets to Disabled.
   b)Fixed system hanged at POST 93h with large memory size with multiple
     add-on cards which consume large PCI memory resources.

9. Updated to Intel MRC v1.20.  Added below BIOS options:
   - High Bandwidth FSB, visible with Woodcrest and Clovertown.

10.Fixed Branch1 not operated in 4:1 interleave for best memory performance.
   -With this fix, memory performance may gain 10% with 4 channels.

11.Updated to BIOS Rev 1.2.

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DBR3A026.ROM	Date:10-02-2006

1. Fixed system hanged upon booting Windows with SIMLP and Dempsey processor.
   (Observed on X7DA8, X7DA3)

2. Supported dynamic SVID&SID configuration per ICH RAID CodeBase.

3. Removed "Debug Only" help message from BIOS Setup.

4. Add "ROM Scan Ordering" in Setup.

------------------------------------------------------------------
DBR39196.ROM	Date:09-19-2006

1. a)IPMI 3rd-LAN's option ROM is configurable by Setup. (All except X7DAL)
   b)Updated Intel AHCI firmware v1.08.

2. Fixed "Sensor Number" displayed as unknown in IPMI menu in Setup.

3. a)Fixed ECC log with zeroed date/time information.
   b)Send DIMM position with ECC error into DMI Event log and IPMI SEL.

4. Stored TCO2_STS byte into CMOS bank 1 offset 78h upon reset.

5. Added PCI-e I/O Performance option in BIOS.

8. Added ACPI NATA object to ESB2 IDE controller.

12.Fixed system hanged at PPM initialization if ACPI is disabled.

------------------------------------------------------------------
DBR38296.ROM	Date:08-29-2006

1. Updated Adaptec ESB2 SATA HostRaid b2130.

2. a)Don't clone MAC address from onboard Lan1 into PepperCon BMC.
   b)Further checked PepperCon firmware readiness if BMC I/O ports ready
     after standby reset. Posted message if BMC FW fails.

3. Onboard Storage's option ROM is configurable by Setup.  Replaced "SCSI"
   string with "Storage" one.

4. Added microcode Rev 060h for Clovertown B-3 stepping(6F7h).

6. Updated to BIOS Rev 1.1c.

7. Fixed system kept reseting with Dempsey after changed frequency ratio.

8. Fixed wrong processor number constructed in MP table if
   CMP set to Disabled.

------------------------------------------------------------------
DBR38216.ROM	Date:08-21-2006

1. Fixed RHEL3 SMP failed to boot SAS drive.

------------------------------------------------------------------
DBR38116.ROM	Date:08-11-2006

1. a)Updated ATi ES1000 video BIOS with yj18686b.cfg.
   b)Updated Intel AHCI firmware v1.07.

2. Displayed correct temperature of Clovertown processors. Each
   Clovertown supports one PECI agent with two domains embedded.
   W83793 chip returns the highest temperature domain when there
   are multiple domains within one PECI agent.
   PECI Agent 4&3 will be hidden.

3. a)Supported to send PCI SERR/PERR SEL into IPMI.  It needs 080406
     IPMI firmware or newer to cooperate with.
   b)Added help message for "PCI Parity Error Forwarding".

4. Wrote SVID&SID into 4th USB controller.

5. a)Supported software method to disable the secondary core of
     Woodcrest/Clovertown processors.
   b)Corrected wrong processor numbers if CMP is disabled.
   c)Double L2 cache size when Clovertown presents.

6. Used a new method to report CMOS checksum bad due to MCH BWA #501592
   resets system and clears checksum bad information.

7. Supported "Direct Cache Access" BIOS option for Woodcrest/Clovertown.

8. Logged upto 10 ECC event logs after system is up. This prevents
   event log pool from expired.

11.Supported EIST for Clovertown processors.

12.Added microcode Rev 033h for Clovertown B-1 stepping(6F5h).

13.Default Date to 07/01/2006 if CMOS low.

14.Fixed Microsoft Vista failed to install and HCT reported
   wrong MBRD structure bytes.

15.Fixed HCT reported USB4._PRW with inproper sleep state.

16.Updated to Intel MRC v1.11 RC3.  Added below BIOS options:
   - High Temp DRAM OP
   - AMB Thermal Sensor
   - Thermal Throttle
   - Global Activation Throttle

18.Hid FAN6 from BIOS Setup for X7DBR series.

19.Allowed PCI-X 133MHz for the bus with SAS and ZCR on X7DBR-3.

20.Forced 3 of x8 link width to workaround wrong strap
   pins on early X7DBR-3 PCBs. It should reduce RMA requests.

21.Updated to BIOS Rev 1.1b.

22.Hardcoded ones in MSR 1AAh<22:21> for Woodcrest per SelfTest.

23.Implemented Blackford BSU v0.77 Specification Clarifications #3

24.Populated the MP table with the full 32 bits of eax/CPUID(1).

25.A system hanging may occur after fixing PCI INT entry missing
   when PCI devices are behind non-Function0 add-on bridge.

------------------------------------------------------------------
DBR37106.ROM	Date:07-10-2006

1. Applied a workaround to support KVM functions with PepperCon BMC.
   *Hardware design changed from USB port#5 to port#6.

2. Update to X7DBR-3/X7DBR-E BIOS Rev 1.1a.

------------------------------------------------------------------
DBR37076.ROM	Date:07-07-2006 Derived from X7DBR-8+ 6236

1. Update Product ID for X7DBR-3 (0928015D9h).

2. Update "X7DBR-3" into SMBIOS Type1~Type2.

3. Update IRQ routing per X7DBR-3.

4. Include official ESB2 HostRaid firmware with proper SVID&SID.

5. Batch build for X7DBR-3.
