BIOS release note

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DHR_8216.ROM	Date:08-21-2006

1. Defaultd Date/Time to 07/01/2006 if CMOS low.

2. Added 2nd set of SMBIOS Type 7 for L1/L2 Cache information.

3. Added "POST Error" option in Setup. It can disable "halt on POST error".

4. Updated to Intel Boot Agent v1.2.36.

7. Update to Supermicro BIOS Rev 2.0a.

8. a)Wrote SVID&SID into onboard VGA for HCT.
   b)Fixed 3-ware AMCC card locked up at POST 49h.

11.Continue to boot if VGA absent.

12.Created a bExtCmosIndex to save/restore the NV1 index
   register during SMI handled.

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DHR_1246.ROM	Date:01-24-2006

1. Corrected a typo in DRAM feature help message.

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DHR_1166.ROM	Date:01-16-2006

1. Corrected a typo in DRAM feature help message.

2. Fixed Post hung at 0Ah if flashing BIOS without /c parameter.

3. Fixed PCIX frequency control no working since B305 release.

4. Default Date to 01/01/2006 if CMOS low.

5. Update to Supermicro BIOS Rev 2.0.

6. MSR 1A0h<6> (L3 Cache Disable) should not be written if no L3 support.

7. A call to pciConfigAccess is missing in the routine pcixConfigBridge.

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DHR_B305.ROM	Date:11-30-2005

1. Fixed 64-bit BARs(PCI memory resources) not initialized correctly.
   *According to customer, Red Hat Linux and Fedora Core x86_64 kernels
    can not accept zeroed high dword BARs.

2. Logged memory bank number which generated ECC error into DMI.
   *Customer wants to isolate which DIMM pair are bad.

3. Display Intel EM64T on POST screen if detected.

4. Supported PCI-Express PM_PME resume event.
   *Most case, PCI-e resume event goes through side-bank singal to south
    bridge especially for S1~S5. Some card vendors utilize the in-bank
    protocol to north bridge for resume upon S1.

5. a)Distributed interrupt requests to different processor threads
     for better performance per MCH BSU.
   b)Fixed WinXP+SP2 installation failed with U320 HostRaid enabled.

6. Default to disable Xeon processor echo TPR feature for better
   performance per Intel.

7. Fixed "System Configutaion Data Read Error" with 6 FC cards.
   *This issue also occurs with add-on bridges and many PCI devices behind.

8. Support Hardware Prefetch feature per CMOS.
   *En/Disable this feature may improve performance depending on application.

9. Update Supermicro BIOS Rev 1.3c.

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DHR_8135.ROM	Date:08-13-2005

1. Update Adaptec Olympia HostRaid v2209 as it fixed console redirection
   disconnection when previous version activated.

2. Allowed console redirection on COM1 with IPMI presented after
   BIOS automaitcally forced to COM2.

3. Add "Default Primary Video Adapter" in Setup. This item allows user
   to selecte the primary between TWO adapters instead of among three
   or more.
   Boards with onboard ATi include "Other" and "Onboard"(Default).
   Boards without onboard ATi include "Other" and "PCI-e x16"(Default).

4. 1)Add "PCI Parity Error Forwarding" in Setup. Defaulted to Disabled. Most
     of operating system can not handle NMI events from PCI parity errors.
   2)Add "ROM Scan Ordering" in Setup. Defaulted to Onboard First. Changing
     this options may gain more option ROM to be shadowed.

5. 2)Added processor entries of secondary thread into MP table.
   3)Reinitialize console redirection after option ROM activated.

6. 1)Update micro-codes for Xeon with 800MHz system bus.
      Update Rev. 17h for Nocona D-0 CPUID F34h.
      Update Rev. 17h for Nocona E-0 CPUID F41h.
      Update Rev. 03h for Nocona G-1 CPUID F49h.
      Update Rev. 05h for Irwindale N-0 CPUID F43h.
      Update Rev. 02h for Irwindale R-0 CPUID F4Ah.
   2)Forced UC mode for E0000-E3FFF MTRR.
   3)Default Date to 07/01/2005 if CMOS low.
   4)Support NMI request from IPMI.

7. Update PXH BSU v1.04.

8. Allow SATA drives to be UDMA capable when IDE controller disabled.

9. De-featured BIOS Recovery Flash. Our flash.bat prevents a wrong
   BIOS from incorrectly being flashed.

10.Update Supermicro BIOS Rev 1.3a.

11.Fixed console redirection overrides A0000h region after clearing
   memory in EBDA.

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DHR_5235.ROM	Date:05-23-2005

1. Downgrade to Adaptec Olypia ICH5R HostRaid firmware.

2. Add "Resume On Modem Ring:" item in Setup.

3. Write SVID&SID into MCH Dev0:Func1.

4. Consistent Pop-up Boot Menu with <F11>.

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DHR_4205.ROM	Date:04-20-2005

1. Fixed wrong frequencies reported for GV3 on E7520 boards.

2. Support Microsoft System-Locked Preinstallation spec.  The string is
   fixed located at F000:FA00h. PLOGO v1.1 Build 050311 can put the
   string into BIOS binary.

3. Fixed onboard IDE/SATA HDDs not found during FreeBsd v5.3+ installaiton.

4. Fixed the delay time after PXH secondary bus reset not enough.

5. Slower memory counting for first 2GB if IPMI card presents.

6. Fixed wrong IRQ entry in MP table for devices behind multiple
   levels of non-embedded P2P bridges.

7. Added High Precision Event Timer(HPET) feature.

8. Pop-up Boot Menu when <F10> key pressed during POST.

9. Fixed Linux crashed when it calls GV3 methods more than once.

10.Moved USB key above any other HDDs if presented.

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DHR_3095.ROM	Date:03-09-2005

1. Apply more POST error logging.
   - Log KBC errors.
   - Log Memory decreased event.

2. Enable DMA controller in MCH for E7520 platforms.

3. a)Support NMI assertion upon PCI SERR# generation.
   b)Force Irwindale to peak speed by Intel's recommendation.

4. Fixed LSI MegaRaid 40-LD can not install Linux.

5. Activate option ROM of add-on cards prior the one of onboard devices.

6. Update Adaptec ICH5R/ESB6300 HostRaid firmware v1255.

7. Add "Memory Remap Function" in BIOS Setup.

8.Update Supermicro BIOS Rev 1.2c.

9. Fixed un-cache SMRAM configured inconsistently between two processors 
   when hyper-threading sets to Disabled.

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DHR_1215.ROM	Date:01-21-2005

1. Enable console redirection on COM2 when IPMI is detected.  BIOS takes
   this action when console redirection WAS disabled.  It intends that
   user can set console redirection on COM1 with IPMI card presented
   if he is not interested in SOL.

2. Expose MCH device0 function1 for ECC reporting per customer demand.

3. Remove processor entries of secondary thread from MP table per Intel
   recommendation.

4. Default to enable processor machine-check feature per Intel.

5. Fixed PCI-e link width set incorrectly in Link Capability register.

6. Fixed Int 15h functions returned incorrect flags.

7. Fixed POST took minutes to complete with multiple P2P bridge cards.

8. Fixed microcode of Xeon-800 N-0 stepping(F43h) never be loaded.

9.a)Default Date to 01/01/2005 if CMOS low.
  b)Micro-codes update to Rev. 12h for Nocona E-0 CPUID F41h.

10.Corrected IRQ routing for MCH root ports in MP table.  WinXP in non-ACPI
   mode can not load chipset driver correctly without this fix.

11.Enable MCH root ports in early POST for lagging Skyhawk.

12.Update Supermicro BIOS Rev 1.2a.

13.Fixed system hanged at POST 93h when "Discrete MTRR Allocation"
   is enabled with 8GB RAM.

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DHR_C174.ROM	Date:12-17-2004

1. Fixed RedHat EL3 hanged at loading ata_piix driver when "Native Mode
   Operation" sets to Serial ATA in BIOS.

2. Changed options of "CPU Temperature Threshold" from 85, 90, 95, 100'C
   to 75, 80, 85, 90'C.  The default is 80'C.

3. Update Supermicro BIOS Rev 1.2.

------------------------------------------------------------------
DHR_C134.ROM	Date:12-13-2004

1. Update micro-codes for Xeon with 800MHz system bus.
     Update Rev. 14h for Nocona D-0 CPUID F34h.
     Update Rev. 0Dh for Nocona E-0 CPUID F41h.

2. Fixed system hanged at 93h with one physical processor.

3. Fixed LSI MegaRAID firmware not responded <Ctrl+M> and <Ctrl+H> keys
   from console redirection terminal.

4. Fixed TM1 feature not enabled for application processors.

------------------------------------------------------------------
DHR_C064.ROM	Date:12-06-2004

1. GV3 bug fixes.  Defaulted to Disabled.

2. Added MCH BIOS specification update revision 1.02.
   a)ICH memory access hang with 32G memory configuration.
   b)Issue secondary bus reset for some ATI PCI Express* x16 graphics bad cards.
   c)Ignore upper six bits to allow parity capable ECC-DIMMs.

3. Fixed software UUID methods ineffective.  Caused by DHR_B014.Fix2.

4. a)Forced Nocona processors with Platform Requirement bit set which
     notices minimal core-to-bus ratio utilization to peak speed.
   b)Forced to memory normal mode when RTC battery lost in case
     in case CMOS has a random value to be sparing/mirroring.
   c)Fixed PCI-e PME failed in S4 state.

5. Fixed system hanged during memtest86 testing.

6. Fixed long PCI initialization when multiple PCI bridge cards.

7. Update Supermicro BIOS Rev 1.1c.

8. Disable SMAlert# pin in case it got set previously to hang the POST.

9. Correct SMBIOS Type17 for dual rank DDR2 memory.

11.Support to Xeon-800MHz upto 6GHz.

12.Revised the code so that NX option is visible when disabled.

13.Fixed TM1 incorrectly enabled with TM2.

14.Support PS/2 port swapping for W83627HF only.

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DHR_B054.ROM	Date:11-05-2004

1. Removed the feature of NMI assertion upon PCI SERR# generation.  Observed
   some boards caused NMI flood with add-on cards and resulted a hung in POST.

2. Fixed only one thread is enabled in Windows when HT is disabled with
   two physical CPUs populated.

3. Moved USB floopy drive above the legacy one.  Thus USB floppy type

4. Don't let OS initialize GV3 when it is disabled in BIOS Setup.

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DHR_B014.ROM	Date:11-01-2004

1. Fixed HCT 12.0 reported errors.  PCI-e platform must define
   MCFG descriptor in ACPI name space.

2. Utilize MAC address from Intel GNIC for programming SMBIOS UUID.  This
   mechanism on BroadCom GNIC is NOT available.

3. Fixed system hanged if pressing <DEL> key within option ROM.

4. Turn off Supermicro LOGO when fan-count is found mismatched
   with BIOS inquiry.

5. Support NMI assertion upon PCI SERR# generation.

6. Fixed LINTIN0 entry incorrectly removed from MP table for MCH C4 stepping.

7. Install Processor Power Management (GV3) for server platforms and defaulted
   to Disabled.

8. ECC Error Type is defaulted to SMI in BIOS Setup.  An ECC error will
   be recorded in event log.  It is also required by memory sparing.

9. Fixed BIOS bugs when PCI hole is 2GB or larger.  BIOS were incorrectly
   reporting "memory error at 1Fh".

10.Configure AC lost recovery setting in early POST.

11.Add "Discrete MTRR Allocation" in BIOS Setup.  nVidia Linux driver
   needs this item.

12.WHQL fixes for IPMI 1.5/2.0.

13.Fixed L2 cache size is not displayed for Irwindale processors.

14.Fixed memory sparing not working when enabled.

15.Update MCH memory reference code v1.04 for mirroring detection.

16.Fixed C1E not enabled for application processor.

17.The system fails in the boot of second bootable cdrom when the first cdrom
   boot fails with a non-bootable disk in it.

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DHR_9254.ROM	Date:09-25-2004

1. Support Phoenix FlashPro for Intel FWH8 and SST 49LF008A.

2. Hardware Monitoring in BIOS Setup with IPMI 1.5 BMC may read
   bad values.

3. Support TM2 and C1E features.
   * TM2 - processor lowers its speed and voltage if overheat.
   * C1E - processor lowers its speed and voltage if OS issues hlt instruction.

4. De-assert SMB_ALERT at early POST.

5. Fixed HCT 11.2 reported errors.

6. Fixed wrong IRQ allocation for add-on card with embedded bridge.

7. Change High/Low limits for -12V at W83792D per SD3 demand.

8. Update micro-codes for Xeon with 800MHz system bus.
     Update Rev. 13h for Nocona D-0 CPUID F34h.
     Update Rev. 09h for Nocona E-0 CPUID F41h.
     Update Rev. 03h for Irwindale N-0 CPUID F43h.

9. Default Date to 07/01/2004 if CMOS low.

10.Video corrupted when inquiring password prior entering BIOS Setup.

11.Support disabling boot devices by <Shift+1> key in BIOS Setup.

12.Updates for "X6DHR-8G/X6DHR-8GS" into SMBIOS Type1 and 2.
   Updates for "X6DHR-8G2/X6DHR-TG" into SMBIOS Type1 and 2.

13.Update PCI-e slot number in BIOS Setup for 1U boards.

14.Supermicro BIOS Rev 1.1b.

15.Install Intel Auto Thermal Management.
   * TCC is disabled at boot time for OS calibrating processor speed.
     TCC is auto-enabled minutes later by BIOS timer.

16.Support BIOS recovery function when the onboard J31 jupmer installed.

17.System hangs at POST 93h when multiple video cards presented with
   4GB more memory.

18.DEVICE_DISABLED does not work for 2nd BEV devices when 1st one
   is not disabled(without leading ! symbol).

19.UCR on COM2 with MB3 results a hung at POST B9h.

20.Fix the bug that the system will hang after logging ECC event
   into DMI.

21.Fixed National Instruments driver resulted a blue screen after
   PCI BIOS32 calls.

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DHR_9094.ROM	Date:09-09-2004

1. Fixed Hardware monitoring not working.

2. Allow onboard NIC to run PCIX 133MHz.

3. Update to Supermicro BIOS Rev 1.1a.

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DHR_8144.ROM	Date:08-14-2004

1. Support Supermicro PLogo utility.  Allow to change LOGO and signo-on
   string at customer sites.

2. Fixed console redirection not connected when flow-control
   sets to None.

3. Fixed incorrect implementation for enhanced MCH PIC workaround.
   Symptoms observed: S1 can not resume by any method, Linux SMP
                      fails to boot.

4. Update to Supermicro BIOS Rev 1.1.

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DHR_8094.ROM	Date:08-09-2004

1. Support SMBIOS Type 38 for IPMI.
   Enhanced detection of IPMI 2.0.

2. Changed Stuck Key message to be warning type so that it won't
   stop POST.

3. Update 1MB into SMBIOS Type 0 for ROM size.

4. Implement MCH PIC mode BWA. Apply to C2 stepping and previous ones.

5. Fixed SOL via IPMI 2.0 had no screen content with W83627 SIO.

6. Hardware Monitoring in BIOS Setup hangs up with IPMI.

7 .Allow to update SMBIOS strings by standard PnP funtion 5xh.

8. WHQL fixes:Unreproted I/O 295h/296h.

9. X6DHR-8G: Correct descriptions of fan headers in BIOS Setup.

10.Update to Supermicro BIOS Rev 1.0c.

11.Console Redirection disconnected at 3455MB during memory count
   with 4GB RAM.

12.System may hang at POST 93h with 12GB RAM.

13.Fixed system hangs after logging ECC event into DMI.

14.Update MCH MRC v1.04.

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DHR_7144.ROM	Date:07-14-2004

1. Updates for "X6DHR-8G" into SMBIOS Type1 and 2.

2. Sign-on string changed to X6DHR-8G/X6DHR-iG.

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DHR_7064.ROM	Date:07-06-2004

1. Fan speed Control modes updated with fine-tuned parameters per
   the approval.

2. Support IPMI 2.0.

3. TM2 Can be supported if following conditions are met.
   - Processor Supports TM2 ( CPUID(1) ECX bit 8 = 1)
   - CPUID is 0F40h and more
   - Platform has dynamic VR
   - Proc Frequency is 3600 Mhz or more

4. Allow 4-sec power button override or install-off per CMOS.

5. Create 'KBC Clock Input' item in Setup.

6. Fixed system hanged at POST 49h with some PCI-E/PCI-X cards.

7. BWA for Serial Over Lan broken.

8. Add micro-code for Nocona E-0 stepping (CPUID F41h).

9. Not allowed USB devices to resume from S4 and S5.  Hardware does not
   supply standby power in both sleep states.

10.Correct PCI slot descriptions in BIOS Setup.

11.Don't display 3.3Vsb in Hardware Monitor.

12.Sign-on string changed to "X6DHR-8XG".

13.System may automatically reset when Quick Boot is disabled
   with 4GB RAM.

14.Removed useless codes of MCH root port detection.

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DHR_6154.ROM	Date:06-15-2004

1. Auto-Fan Control supports Server sku with pre-set parameters.
   Also update its help message.

2. Rise CPU thresholes to refect proper Nocona termperature trip points.

3. Re-model BIOS Setup.

4. X6DHR: Correct onboard VGA IRQ entries in MP table.

------------------------------------------------------------------
DHR_6044.ROM	Date:06-04-2004

1. Auto-Fan Control option utilizes either 4-pin wire or 3-pin wire
   for selections.  Also update its help message.

2. Update event log message for wrong memory population.

3. Display DRAM type and Hyper-Threading status.
	
4. Display the numbers of logical processors presented on POST screen.

5. Fix: BIOS does not display messages for JBT1 event and RTC low.

6. Update MCH memory reference code 1.03 version.

7. Default to enable Supermicro LOGO.

8. Fixed system hanged at POST 49h with some combinatons of
   card population.  Update PXH BIOS reference code version v1.0.

9. Fixed bus number not updated correctly in MP table.

10.Don't clear chassis intrusion bit of W792D.

11.Update to W627HF for X6DHR-8XG and X6DH8-G PCB v1.1.

12.Enable GPIO port1 for detecting power fail.

13.New CPU Features implementation for C1 Enhanced Mode and
   No Execute Mode Mem Protection.

14.Fixed PCI 66MHz card can only run PCI 33MHz.

15.Create an BIOS option for memory mirror and sparing.

16.Update to Supermicro BIOS Rev 1.0.

17.Implement ICH5 WW19 recommendation.

18.Fixed system hanging at 93h when hyper-threading is disabled with 4GB.

19.Enable PME interrupt of PCI-Express.

20.Multi-bits ECC can't generate SMI by testing DIMM modules.

21.Allow to boot with 8 DDR-333 DIMMs populated.

22.Boot DDR1-400 DIMMs with DDR-333 timing.

23.Update micro-code Rev. 0Eh for Nocona D0 stepping.

24.Fixed failed detection with some slave-only IDE devices.

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DHR_5104.ROM	Date:05-10-2004

1. Fixed Win2003 installer hangs up during examining hardware.

2. Auto-Fan enhanced. BIOS will save detected fan-count when Auto-Fan
   is first enabled. BIOS compares new detected fan-count with the one
   saved in CMOS each time POST occurs.  Fans remain full speed once
   the comparison results not equal unless user accepts new fan-count
   or 10-sec time-out happens.

3. Update Memory reference code v1.00.

4. Disable Hyper-Threading through MCH's strap pin.

5. Update BSU/SU for PXH.

6. Hardware Monitorig not accurate with W792D C version.

7. Show N/A when CPU2 absent

8. Bug fixes for .Net WHQL.

9. ASL code update.

10.a)DMI event logging.
   b)Send only differences with UCR.

11.Configure GPIO properly in early POST.

12.Don't support auto-PLLSEL on X6DHR.

13.Update micro-code for Nocona D0 stepping.

14.Some USB flash drive take too long for identification during POST.

15.Console redirection doesn't work during ROM activation.  For some
   reason, this file was not check-in in CORE_3224 label.

------------------------------------------------------------------
DHR_4104.ROM	Date:04-10-2004

1. Include official SATA HostRaid firmware for ICH5.

2. Allowed to boot with wrong dula-rank memory population.

3. Program SVID/SID into MCH Bus0:Dev0:Func1 per WHQL.

4. Update MCH BSU v0.75.

5. Fix: Wrong configuration for PXH Bus B.

6. Correct SMBIOS Type0, 4, 7, 9, 11, 16, 19 and 20.

7. Allowed to auto-switch PLLSEL for DDR266/DDR333 by W627 GPO<45,31>.

8. Update micro-code for Nocona D-0 stepping.	

9. Update MCH MRC v0.86.

10.Migrate to Intel 8Mb FWH8 for X6DHR.

11.Updates IRQ routing for X6DHR-8XG PCB v1.01.

12.Update MCH sightings report Rev 1.18 #62 for X6DHR.

13.Fix: Standard PCI-E write Word/Dword procedure incorrect.

14.Added an NMI handler in compliance with Intel Netburst BIOS
   Writer's Guide Rev 1.6

15.CDROM doesn't boot normally with some RAID controllers.

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DHR_3224.ROM	Date:03-22-2004

1. Add "Clock Spectrum Feature" in BIOS Setup.

2. Default to Disable "MCH Compliance 1.0 BWA".

3. Fix: Bus Mastering of PCI slots is not controlled by BIOS Setup.

4. Fix: Activation of Option-ROM on bridge-embedded card is not
   controlled by BIOS Setup item.

5. Fixed missing PCI interrupt entries in legacy MP table for devices
   behind non-function0 bridge.

6. a)Fixed dramatically rapid voltage switching for FAN-64 when Auto-Fan
     is enabled.
   b)Support Smart Fan II control for CPU2.
   c)Use W83792D pin47 for watch dog feature.

7. Hard-coded parameters for Auto-Fan control with W83792D solution.

8. Fixed missing wake notification for onboard GNIC.

9. Fix: System hangs at POST 0Ah on some bring-up boards with CMOS checksum error.

10.Console redirection don't work during ROM activation.

11.Update PXH initialization reference code version 0.72.

12.Fix: COM and LPT ports disabled in BIOS Setup not hidden in ACPI OS.

13.Remove Smart Fan II tuning items from BIOS Setup.

14.Access W83792D via SMBus 05Eh per hardware change.

15.Update MCH memory reference code 0.8x version.

16.Update cache kernel code.

17.Support IA-32e for Nocona processors.

18.Support PCI-Express hot plug.

19.Open some setup items for memory RAS feature control.

20.Modified string to fit inside setup help window pane for TM2.

------------------------------------------------------------------
DHR_3034.ROM	Date:03-03-2004

1. a)Don't halt for keyboard error when it is.
   b)Fix: BIOS does not display error message if JBT1 is short
     previously and if CMOS checksum is wrong.

2. Turn off the Power Led when power off from non-ACPI and ACPI OS(Winbond SIO).

3. Allow JWOR and JOL jumers to wake up system.

4. Remove "Adaptec HostRAID Feature" from BIOS Setup.  The firmware
   can manage both modes by itself.

5. Write SVID and SID into ICH5 SATA and AC97 controllers.

6. Enable the 4th USB controller and USB legacy.

7. Display PCI-X bus speed in summary table.

8. Add Thyrst(Low Limitation) for CPU1/CPU2(Winbond SIO).

9. Support AC lost recovery feature(Winbond SIO).

10.Fixed onboard NIC can not wake system up.

11.Fixed failed detection with slave-only IDE device.

12.Update U320 HostRaid firmware v4.30.

13.a)Display BIOS build-date in BIOS Setup.
   b)Display current processor speed in BIOS Setup.

14.Jumperless control for PCI-X bus frequency decoded by 2nd PXH(X6DHR).

15.Drive GPO25 high at power-on.

16.Allow DDR333 populated from farthest DIMM(DIMM #1 at board end) on 4-pair platform.

17.Add PCI-E MCH B0 stepping BIOS workaround in BIOS Setup.  Integrate
   1.0 compatible mode into each PCI-E port.

18.Stable detection for PCI-E training status.

19.Fixed console redirection halt with 4GB memory.

------------------------------------------------------------------
DHR_2184.ROM	Date:02-18-2004

1. First Release.
