X10DSN-TS release note
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 CPU Microcode                              | Option ROM/uEFi driver                            | Intel RC/LT-SX/ME
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 CPUID FAMILY                               | Aspeed VBIOS                         : 1.02.07    | RC Package : 4.0.0
 306F1 Haswell-EP B0/L0          : 00000014 | Intel SATA RAID Option ROM           : 4.5.0.1012 | SPS        : 3.1.3.38
 306F2 Haswell-EP C0,1/M0,1/R2   : 00000039 | Intel RSTe sSATA Option ROM          : 4.5.0.1012 | BIOS ACM   : 20160523 (3.1.0)
 406F0 Broadwell-EP A0,1         : 00000014 | Intel Boot Agent Giga LAN            : 1.5.72     | SINIT ACM  : 20160526 (3.1.0)
 406F1 Broadwell-EP B0/M0/R0     : 0B00001F | Intel Boot Agent 10G LAN             : 2.3.46     |
                                            | Intel FCoE Option ROM                : 1.8.04     |
                                            | Intel iSCSI Option ROM               : 2.8.16     |
                                            | Intel Giga UEFI x64 PCI-E LAN driver : 6.9.07     |
                                            | Intel 10G UEFI x64 LAN driver        : 5.1.19     |
                                            | Intel RSTe SATA UEFI driver          : 4.5.0.1012 |
                                            | Intel RSTe sSATA UEFI driver         : 4.5.0.1012 |
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 BIOS feature             |  Support
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 OOB Flash BIOS           |     Y
 OOB Update Setting       |     Y
 OOB Change SMBIOS        |     Y
 InBand Flash BIOS        |     Y
 InBand Update Setting    |     Y
 InBand Change SMBIOS     |     Y
 InBand SMI E7h supported |     Y
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 SW ECO Caused By         |  Status
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 BIOS/IPMI Customization  |     N
 HW Vendor Updates        |     N
 BIOS/IPMI Workaround     |     N
 BIOS/IPMI Vendor Updates |     Y
 BIOS/IPMI Enhancements   |     Y
 BIOS/IPMI Bug fixes      |     Y
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 BIOS          : X10DSN7.211      Release Date  : 02/11/2017
 BIOS Revision : 2.0             BIOS Engineer : Leon Xu
 BIOS Checksum : 68DF1916h
 BIOS Change:

1. Update Broadwell-EP RC 4.0.0 PLR8 release.
   Description: Update Grantley Refresh RC 4.0.0 Post Launch Release 8 (PLR8) version for below issues.
                  Modify the Reference Code Revision for BDX-EP to 4.0.0
                  5003486: On S3/warm reset exit uncorrectable memory errors can be observed
                Below issue are fixed at RC 3.9.0 PLR7 release.   
                  5003452: PPR failure due to the MRS snooping command in the BIOS PPR sequence.
                  5003423: SODIMM Rawcard-H t_rrdd/t_rrdr +1.
   Validation:  a) Use PCI.exe to check Bus<0x7F,0xFF>/Device<0x10>/Function<0x07>/Reg<0x90>.
                   Please check Bus<0x7Fh> if two CPU attached and Bus<0xFFh> if only one CPU attached.
                   // [31:24] = Major revision number
                   // [23:16] = Minor revision number
                   // [15:8]  = Release Candidate number
		b) Validate standard feature with Broadwell-EP/Haswell-EP CPU.
		c) Validate CPU performance like LINPACK and others.

2. Update Intel Server Platform Services 3.1.3.38 PLR7 for Grantley Refresh Platforms
   Description: This is Post Launch Release 7 for Grantley Refresh Platforms for below issues.
                CCG0100857146 System unexpected shutdown with SPS FW exception error.
   Validation:  a)Enter Setup menu to check the ME revision is 3.1.3.38 and current state is operational.
                b)Check SPS functions like Node management.

3. Update CPU microcode  SRV_P_181 for Broadwell-EP B0/M0/R0.
   Description: Update Broadwell-EP B0/M0/R0 CPU uCode MEF406F1_0B00001F
                BDF78: Writing The IIO_LLC_WAYS MSR Results in an Incorrect Value
                BDF79: Turbo May Be Delayed After Exiting C6 When Using HWP
                BDF81 Interrupt Remapping May Lead to a System Hang.
                BDF83 Bi-Directional PCIe* Posted Transactions May Lead to System Hang.
   Validation:  Check Broadwell-EP B0/M0/R0 CPU  microcode version is 0x0B00001F.

4. Update CPU microcode SRV_P_182 for Haswell-EP C0,1/M0,1/R2.
   Description: Update Haswell-EP C0,1/M0,1/R2 CPU uCode M6F306F2_00000039.
                HSE116 Interrupt Remapping May Lead to a System Hang.   
   Validation: Check Haswell-EP C0,1/M0,1/R2 CPU microcode version is 0x39

5. Patch BIOS can't identify VPD data of AOC-S25G-m2S and AOC-S100G-m2C.
   Description: The VPD data of AOC-S25G-m2S and AOC-S100G-m2C can't report to SMBIOS Type 40.
   Validation : Check SMBIOS Type 40 can see the VPD information of AOC-S25G-m2S and AOC-S100G-m2C when plugged it.

6. Fixed system hang when plug the addon card which contained the non SMC format VPD data.
   Description: system hang when plug the addon card which contained the non SMC format VPD data.
   Validation : Check system can boot up normally when plug Mellanox CX314A LAN card.

7. Fixed "Processor Frequency" cannot be changed when setting "Boot performance mode" to "Max Efficient" by AMI BCP.
   Description: CPU POST frequency is always shown Max Non-Turbo frequency in BIOS setup and POST screen.
   Validation: a) Using AMI BCP to change BIOS setup Advanced -> CPU Configuration -> Advanced Power Management Configuration -> Power Technology to "Custom".
               b) Using AMI BCP to change BIOS setup Advanced -> CPU Configuration -> Advanced Power Management Configuration -> CPU P State Control -> Boot performance mode to "Max Efficient".
               c) Check "Processor Frequency" in BIOS setup and POST screen.

8. Fix running "GetCurrentBiosCfgTextFile" by sum return error after AMIBCP modified BIOS Setup.
   Description: Fix running "GetCurrentBiosCfgTextFile" by sum return error after AMIBCP modified BIOS Setup.
   Validation:  1. Modify Wait For "F1" If Error in BIOS ROM by AMIBCP.
                2. Flash the BIOS ROM into machine and boot to OS.
                3. Execute remote command "./sum -i xx.xx.xx.xx -u ADMIN -p ADMIN -c GetCurrentBiosCfgTextFile --file current.txt --overwrite".
                4. No errors.

9. System hang at POST 0xB2 when plug Mellanox MCX311a and MCX312C-XCCT.
   Description: Invalid VPD data cause system hang.
   Validation: 1) Plugged Mellanox MCX311a or MCX312C-XCCT and boot the system, system can boot to OS successfully.
               2) Plugged other AOC LAN card with valid VPD date and boot the system, system can boot to OS successfully.

10.Fix hang 0xA9 when GPNV event log is full.
   Description: The NVRAM will crash and got SMM MCE error. (Update AMI EIP238804)
   Validation : Run BIOS automation test for GPNV event log full test case.

11.Correct MECI's help strings.
   Description: Should be "Multiple" instead of "Mutiple"
   Validation: Enter BIOS setup menu to check if MECI help strings has any typo.
               It should be "Multiple Event Count Increment:........."

12.Force MPL to 128B for NVMe device and its uplink P2P
   Description: When NVMe drive being plugged back, the MPL will keep 128B even it was 256B previously
   Validation: Compare NVMe device control register bit{5:7] (Ex. BUS 0: DEVICE 1, 2, 3: FUNCTION 0-1, 0-3, 0-3: OFFSET 0x98)
               MPL before NVMe plugged out and then plugged in

13.Support VPD info and AssetInfo in SMBIOS type 40.
   Description: Build VPD info and AssetInfo into SMBIOS type 40 for software tool.
   Validation: 1.Plug a LAN card which has VPD data.
               2.Boot to DOS, use RU to find the SMBIOS Type 9 handle number of this LAN card.
               3.Use RU and the Type 9 handle number(referenced handle) to find the corresponding SMBIOS Type 40.
               4.USe RU to check VPD/AssetInfo present in the corresponding SMBIOS Type40.

14.Let MECI (Multiple Event Count), METW (Multiple Event Time Window) can work with Memory correct error report and Pcie error report.
   Description: Default METW is 60 min, MECI is 1. It mean that allow one count for the same error event report in 60 minute. 
   Validation : 1.Turn on MCE by cburn MCEON. 
                2.Inject Memory correctable to 100 count in the same DIMM location by IDK or MEI in 59 min.
                3 Check SMBIOS Event log and IPMI event log. Will only see one memory correctable log.

15. Set NUMA to disable as default.
   Description: Set NUMA to disable as default. 
   Validation : None.
   
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BIOS : X10DSN6.A28                      Release Date  : 10/28/2016
BIOS revision: 2.0                  	BIOS Engineer : Leon Xu
BIOS Checksum: 6866AAF7<h>
BIOS Change:

1. Implement PCIE settings.

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BIOS : X10DSN6.910                      Release Date  : 09/10/2016
BIOS revision: 2.0                  	BIOS Engineer : Leon Xu
BIOS Checksum: 036846E6h 
BIOS Change:

1. Inital BIOS.
2. Implement PCIE settings.
